Table of Contents
More details about the hardware
Intro
We want to encourage you to tinker with your rad1o. Write your own software or build a pluggable hardware. Surprise with your creative ideas!
Several people contacted us about producing rad1o for other occasions. All necessary information is on github and we're happy to help.
Schematic
CPU
Name: NXP LPC4330FET180
Description: 32-bit ARM Cortex-M4 microcontroller with Cortex-M0 coprocessor, 264KB (128kB + 72kB + 2x32kB) SRAM, 2x USB 2.0 Device/Host/OTG
Links: Vendor Product Page NXP Datasheet NXP Manual ARM Cortex M4 Technical Reference Manual
CPLD
Name: XILINX XC2C64A
Description: CoolRunner-II CPLD 64-macrocell Low Power CPLD, Links: Datasheet
LCD
rad1o comes with a color display:
Name: Nokia 6100
Description: Nokia 6100 - 130×130 LCD
Controller: NXP PCF8833 Datasheet or Epson S1D15G10 Datasheet
Connector: Hirose DF23-10DS Datasheet
RF
HackRF style SDR transceiver, built around the Maxim MAX2837 Wimax Transceiver with an external mixer for up and down converting.
Frequency range from 50 Mhz to 4 GHz (you can maybe operate it up to 6 GHz, but the RF switches and amps are then out of spec).
There are three differnt versions of clock generator ic used SI5351 A / SI5351 B / SI5351 C
Differences on page 18 and following pages.
SI5351 C ⇒ Potentially a clock input can be added
Battery
Description: Custom made 3.7V 1500-2000 mAh rechargeable LiPo battery
Dataflash
Name: W25Q16DVSNIG
Description: Serial interface flash memory, 16Mbit of memory organized as 8192 pages of 256 bytes
USB
USB0 Micro USB (2.0) socket (Bootloader can load new Firmware here) USB1 Micro USB (2.0) socket
Audio
4 Pin 3,5mm Headset Connector (Iphone Pinout configured)
| Pin | Name | Description |
|---|---|---|
| Tip | left | Audio out (bridged mono) |
| Ring1 | right | Audio out (bridged mono) |
| Ring2 | GND | Ground |
| Base | mic | Audio in (3.3V Bias) |
LEDs
| LED | Port | Location | Color |
|---|---|---|---|
| LD801 | P4_1 | bottom left | green |
| LD802 | P4_2 | bottom right | green |
| LD803 | P6_12 | left | green |
| LD804 | PB_6 | top | red |
Misc
One 5 way switch (Datasheet)
Optional Interfaces
(All not populated)
X301 External Antenna (SMA)
| Pin | Name | Description |
|---|---|---|
| Pin | RF | RF In/Out |
| Ring | AGND | Analog Ground |
X201 External Clock out (SMA)
| Pin | Name | Description |
|---|---|---|
| Pin | CLK3 | Clock Out 3 from Clock Generator |
| Ring | AGND | Analog Ground |
JTAG (2x05 male socket (2.54mm/100mil))
| Pin | Name | Description |
|---|---|---|
| 1 | VCC | 3.3V |
| 2 | TMS | Jtag TMS |
| 3 | GND | Ground |
| 4 | TCK | Jtag TCK |
| 5 | GND | Ground |
| 6 | TDO | Jtag TDO |
| 7 | nc | not connected |
| 8 | TDI | Jtag TDI |
| 9 | GND | Ground |
| 10 | Reset | Reset ARM |
X1 I/O (2x10 male socket SMD (2.54mm/100mil))
| Pin | Name | Description |
|---|---|---|
| 1 | nc | not connected |
| 2 | nc | not connected |
| 3 | nc | not connected |
| 4 | nc | not connected |
| 5 | VCC | 3.3V |
| 6 | SD_POW | |
| 7 | SD_VOLT0 | |
| 8 | GND | Ground |
| 9 | B2AUX2 | CPLD Bank2-2 |
| 10 | B2AUX1 | CPLD Bank2-1 |
| 11 | B1AUX14 | CPLD Bank1-14 |
| 12 | B1AUX13 | CPLD Bank1-13 |
| 13 | CPLD_TCK | CPLD TCK |
| 14 | B2F3M2 | CPLD Bank2 F3 M2 |
| 15 | CPLD_TDI | CPLD TDI |
| 16 | B2F3M6 | CPLD Bank2 F3 M6 |
| 17 | B2F3M21 | CPLD Bank2 F3 M12 |
| 18 | B2F3M4 | CPLD Bank2 F3 M4 |
| 19 | CPLD_TDO | CPLD TDO |
| 20 | CPLD_TMS | CPLD TMS |
GPIO I/O (2x11 male socket (2.54mm/100mil))
| Pin | Name | Description |
|---|---|---|
| 1 | VIN | Input Voltage from USB/Battery |
| 2 | RTC_ALARM | Real Time Clock Alarm Out |
| 3 | VCC | 3.3V |
| 4 | WAKEUP | CPU Wake Up |
| 5 | GPIO3_8 | CPU GPIO 3-8 |
| 6 | GPIO3_9 | CPU GPIO 3-9 |
| 7 | GPIO3_10 | CPU GPIO 3-10 |
| 8 | GPIO3_11 | CPU GPIO 3-11 |
| 9 | GPIO3_12 | CPU GPIO 3-12 |
| 10 | GPIO3_13 | CPU GPIO 3-13 |
| 11 | GPIO3_14 | CPU GPIO 3-14 |
| 12 | GPIO3_15 | CPU GPIO 3-15 |
| 13 | GND | Ground |
| 14 | ADC1_6 | CDU ADC1-6 |
| 15 | GND | Ground |
| 16 | ADC0_2 | CDU ADC0-2 |
| 17 | nc | not connected |
| 18 | ADC0_5 | CDU ADC0-5 |
| 19 | GND | Ground |
| 20 | ADC0_0 | CDU ADC0-0 |
| 21 | BAT+ | Battery + |
| 22 | VBAT | Not Used |
CPLD I/O (2x10 male socket (2.54mm/100mil))
| Pin | Name | Description |
|---|---|---|
| 1 | VCC | 3.3V |
| 2 | GND | Ground |
| 3 | B2AUX16 | CPLD Bank2 AUX16 |
| 4 | B2AUX15 | CPLD Bank2 AUX15 |
| 5 | B2AUX14 | CPLD Bank2 AUX14 |
| 6 | B2AUX13 | CPLD Bank2 AUX13 |
| 7 | B2AUX12 | CPLD Bank2 AUX12 |
| 8 | B2AUX11 | CPLD Bank2 AUX11 |
| 9 | B2AUX10 | CPLD Bank2 AUX10 |
| 10 | B2AUX9 | CPLD Bank2 AUX9 |
| 11 | B2AUX8 | CPLD Bank2 AUX8 |
| 12 | B2AUX7 | CPLD Bank2 AUX7 |
| 13 | B2AUX6 | CPLD Bank2 AUX6 |
| 14 | B2AUX5 | CPLD Bank2 AUX5 |
| 15 | B2AUX4 | CPLD Bank2 AUX4 |
| 16 | B2AUX3 | CPLD Bank2 AUX3 |
| 17 | GCK2 | Clock Generator Out 2 |
| 18 | GCK1 | Clock Generator Out 1 |
| 19 | GCK0 | Clock Generator Out 0 |
| 20 | GND | Ground |
I2SO I/O (2x13 male socket (2.54mm/100mil))
| Pin | Name | Description |
|---|---|---|
| 1 | CLKIN | not used |
| 2 | CLKOUT | not used |
| 3 | RESET | CPU Reset |
| 4 | GND | Ground |
| 5 | I2C1_SCL | I2C1 Serial Clock |
| 6 | I2C1_SDA | I2C1 Serial Data |
| 7 | SPIFL_MISO | SPI Flash Master in Slave Out (solder R218 for use) |
| 8 | SPIFL_SCK | SPI Flash Serial Clock (solder R217 for use) |
| 9 | SPIFL_MOSI | SPI Flash Slave In Slave Out (solder R219 for use) |
| 10 | GND | Ground |
| 11 | VCC | VCC 3.3 V |
| 12 | I2SO_RX_SCK | I2S RX Serial Clock |
| 13 | I2SO_RX_SDA | I2S RX Serial DATA Not used |
| 14 | I2SO_RX_MCLK | I2S RX M Clock |
| 15 | I2SO_RX_WS | I2S RX WS |
| 16 | I2SO_TX_SCK | I2S TX Serial Clock |
| 17 | I2SO_RX_MCLK | I2S TX M Clock |
| 18 | GND | Ground |
| 19 | U0_RXD | Uart 0 RX Data |
| 20 | U0_TXD | Uart 0 TX Data |
| 21 | P2_9 | Battery + |
| 22 | P2_13 | Not Used |
| 23 | P2_8 | Ground |
| 24 | I2C0_SDA | I2C 0 Serial Data |
| 25 | I2C0_SCL | I2C 0 Serial Clock |
| 26 | VDD | VDD RF 3.3 V Supply |
ISP (1x06 male socket (2.54mm/100mil))
| Pin | Name | Description |
|---|---|---|
| 1 | GND | Ground |
| 2 | ISP | CPU ISP |
| 3 | n.c | Not Connected |
| 4 | U0_RXD | Uart 0 RX Data |
| 5 | U0_TXD | Uart 0 TX Data |
| 6 | RESET | CPU RESET |